Performance Ananlysis of Speeded-Up High-Speed Packet Switches

In this paper, we study the performance of high-speed packet switches, where the switch fabric operates at a slightly higher speed than the links, i.e., a speeded-up switch. As link speeds keep increasing, the speedup of N (number of links) needed for pure output queueing (which is the best) becomes a significant technical challenge. This is one of the main reasons for the renewed interest in moderately speeded-up switch fabrics. The aim of this paper is to highlight the result that only a moderate speed-up factor (less than two) is sufficient to achieve full input link utilization. In particular, we emphasize that this holds, even without relying on a central switch controller making intelligent decisions on which packets to schedule through the switch. As shown in recent works, i.e., [10, 12, 8, 2, 11], there are clearly benefits to using intelligent controllers, but they do come at a cost. Instead, in this paper we focus on what can be achieved by relying simply on switch speedup. We do so by means of analysis and simulations for average queue length in switches with speedup. We also present simulation results on delay performance.